Low Voltage Differential Switching (LVDS) is a known ANSI standard. In the prior art, LVDS output stages have been implemented in CMOS, bipolar, and BiCMOS processes. However, as the power supply voltage levels decrease from 3.3V to 2.5V, bipolar implementations become more difficult.
FIG. 1 shows a typical example of a prior art LVDS bipolar output stage. The input differential transistor pair Q101-Q102 are bipolar PNP transistors. The tail current for this differential transistor pair comes from a bipolar transistor Q103 and the amount of the tail current is controlled by a current mirror Q104. The LVDS standards require the outputs have offset voltage level from 1.125V to 1.275V with 250 mV to 400 mV swing. Also, the power supply voltage level needs to be high enough to avoid saturating the transistors in the differential pair Q101-Q102, and the current source Q103. For many processes, it is nearly impossible to use 2.5V power supply voltage in this implementation. And since PNP bipolar transistors are used, the circuit operates at a less than optimal speed for data and RF applications.
FIG. 2 shows another form of output circuit known in the art, a differential multiplexer. In this configuration, the input differential pair Q202-Q202b or Q203-Q203b, and the selection differential pair Q201-Q201b are stacked together. A sufficiently high power supply voltage is needed in such a configuration to avoid device saturation and is difficult to implement with a 2.5V power supply voltage. Another disadvantage of this configuration is that the select signal S-Sb can couple to the output through junction capacitance of the selection differential pair Q201-Q201b thereby producing an output signal that is corrupted for some time following the select transitions.